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Platinum OFET Test Chips, High Density

Substrates and Fabrication

Product Code S403A1
Price £150 ex. VAT

Our new range of robust and reusable platinum test chips are designed to save you time and money.

The OFETs were patterned via photolithography, meaning very narrow channel lengths are achievable.

The platinum is sputtered onto a titanium adhesion layer, to provide an extremely robust contact and channel allowing it to withstand cleaning procedures such as solvent sonication, plasma etching, and swabbing. This allows the test chips to be reused multiple times for testing various materials saving a significant amount of time and money.

NOTE: Patterning using photolithography leaves exposed edges of the titanium adhesion layer. The consequence of this is that charge injection into the semiconducting layer can occur from the adhesion layer boundary instead of the platinum. Therefore these devices are recommend for single-crystal or single-flake materials that can sit on top of the electrode and span the electrode gap.

Mobility screening is made quick and simple with our prefabricated high density test chips, by depositing your semiconductor directly onto the surface you can create up to 20 OFETs on a single chip. In addition when using our high-density OFET test board you can test an entire chip in as little as 3 minutes reducing the overall time of both fabrication and measurement.

Product code Channel geometry Channel width Channel length Electrode pairs Quantity Price
S403A1 Linear 1 mm 2-10 μm Variable 20 1 £150
S403A2 Linear 1 mm 4-10 μm Variable 16 (minimum) 1 £90

Looking for prefabricated OFET test chips on silicon/silicon oxide substrates?

We have discontinued our prefabricated OFET test chips on silicon/silicon oxide substrates (high and low density). If you are not sure if our newer reusable platinum OFET test chips will be suitable for your application, please contact us for advice.

User Manual High Density Platinum OFET Test Chips User Manual


Substrate / Gate Silicon (p-doped)
Gate dielectric 300 nm thermally grown silicon dioxide
Source-Drain electrodes Platinum (100 nm) / Titanium adhesion layer (5 nm)
Depostion method Plasma sputtering
Patterning method Photolithography


Ossila High Density Substrates feature up to 20 OFETs which can benefit your research in a number of ways. Firstly, production cost is reduced as a result of a higher volume of OFETs per substrate compared to the low density equivalents. This can help to stretch your budget to allow you to produce and test larger numbers of OFETs.

Secondly, producing OFETs is a far faster and less laborious process. Fabrication time is reduced by up to 50% when using prefabricated high density OFETs, freeing up more time to test the devices. As a result of this, greater volumes of statistics can be produced which in turn can provide more robust and reliable research.

Furthermore, OFET variability is reduced since a larger number of OFETs are produced with each fabrication. At Ossila we have optimised the fabrication process in order to produce consistently high quality substrates. In this respect, using our prefabricated substrates rather than fabricating your own can help you to gather more reliable data to benefit your research project.

Prefabricated high density substrates are ideal for mobility testing as they enable swift, efficient testing of high volumes of OFETs. The Ossila high-density OFET test board has been designed for this purpose.

Rather than using a mechanical probe station to test OFETs, which is a delicate and time-consuming process, the high density test board allows testing of multiple OFETs at one time; simply drop the substrate into the test slot, secure the push-fit lid and connect the board via its BNC connectors to an array of test equipment.

The board has been intelligently designed to reduce external noise, leakage current and stray capacitance in order to provide reliable and precise low-current testing.

High density FET mobility test board
The Ossila High Density OFET Test Board, designed for rapid, reliable testing of multiple OFETs.


We fabricate our platinum test chips from p-doped silicon substrates. An insulating 300 nm silicon oxide gate dielectric is first grown on both sides of the silicon. The source and drain contacts consist of a 5 nm titanium adhesion layer below 100 nm of platinum. A platinum gate contact is also deposited along one edge of each substrate.

It is essential that there is an electrical connection between the gate contact and the p-doped silicon on the substrate sides. When the substrates are diced, a weak electrical connection is formed, however this can be easily removed when cleaning the substrate. We recommend applying silver (conductive) paint along and around the gate contact edge so that a more robust connection is made with the substrate edge.

Structure of prefabricated platinum test chip
Structure of prefabricated silicon/silicon oxide substrates

For individual details and dimension drawings of each substrate type see below.

Linear variable channel length substrates (S403 & S404)

Geometry Linear
Arrangement (S403) 20 electrode pairs, 5 channel widths
Arrangement (S404) 16 electrode pairs minimum, 4 channel widths minimum*
Channel width 1 mm
Channel lengths 2 (S403A1 only), 4, 6, 8, and 10 µm

*Please note that the fabrication and layout of S403A1 and S403A2 is identical, however one or more of the 2 µm channels may not be fully resolved on the S403A2 substrates (as highlighted with the red dotted border in the figure below). All four 2 µm channels are present on the S403A1 substrates. The S403A2 substrates may have some cosmetic defects (edge chips, minor surface scratches) that will not affect device performance.

Schematic showing which channels may not be present in the S404 substrates
Schematic showing channels on the platinum OFET test chips
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