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Product Code E305-SPC
Price $390

Low Density Gate Deposition Mask

Enabling good deposition resolution


An evaporation mask for deposition of gate contacts. For use with the low density OFET system. A 100 μm standoff-spacer ensures that the mask does not touch the substrate while still enabling good deposition resolution.

Mask with direct contact (no spacer): For sputtering and other non-directional deposition systems, as well as for thermal deposition systems with oblique angles or a very short throw, we recommend the use of the direct contact mask to get well-defined edges.

Mask with 100 μm spacer: For normal thermal evaporation systems we recommend the use of masks with the 100 μm spacer to help avoid scratches and allow better out-gassing.

Datasheet


Size 75 mm x 75 mm (2.95" x 2.95")
Width 1.7mm without spacer, 1.8mm with spacer (exc. bolts)
Material Stainless steel
Capacity 12 substrates
Dimensioned diagram of the low density OFET gate mask.
Dimensioned diagram of the low density OFET gate mask.

System Overview


The low density fabrication system has four different masks available (source-drain, gate deposition, active area deposition, and insulator deposition) to allow the fabrication of devices in any geometry (top/bottom gates and top/bottom source-drain). The diagrams below show the features on each of the individual masks as well as how they fit together on a substrate.

OFET evaporation stack low density
Schematic diagram showing how the different evaporation masks fit together on a device. For back-gate Si/SiO2 substrates, the insulator and gate masks are not required as the gate contacts on the source-drain mask wrap around to contact the central Si layer of the substrate.
Ossila low density evaporation masks
Left: an FET using the low density evaporation masks. Right: a back-gated FET using Si/SO2 substrates.

Note that silicon oxide substrates do not need a gate mask which simplifies fabrication, however the use of a gate mask with quartz-glass substrates can allow lower operating voltages and lower parasitic capacitance.

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